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现本人正在作毕业设计, 有关computer architecture方面的, cache design. 涉及verilog语言, trace等. 因经验不足请教高手, 重谢. 请联系: zi_moon@hotmail.com.

moon98 (月儿弯弯)
(#356327@0)
2002-2-2 -04:00
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Back To Topic: 现本人正在作毕业设计, 有关computer architecture方面的, cache design. 涉及verilog语言, trace等. 因经验不足请教高手, 重谢. 请联系: zi_moon@hotmail.com.

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